PXD20RM Datasheet, PDF (621/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

at address 0x100. The multiple mapping allows the DMA to get all information with a 64-byte transfer,
but some decompression is needed on decoding the data, while the CPU can read the 19 registers, and just
mask out the upper 8 bits to get relevant information.
Table 14-10. Monitor Counter Descriptions
Field
Description
performance monitor 1 read counter Every time the PowerPC performs a read access, whose address is higher or equal
than the performance monitor 1 address low, and lower than the performance monitor
1 address high, this counter is incremented¹.
performance monitor 2 read counter Every time the PowerPC performs a read access, whose address is higher or equal
than the performance monitor 2 address low, and lower than the performance monitor
2 address high, this counter is incremented¹.
performance monitor 1 write counter Every time the PowerPC performs a write access, whose address is higher or equal
than the performance monitor 1 address low, and lower than the performance monitor
1 address high, this counter is incremented¹.
performance monitor 2 write counter
granted ACK counter 0
granted ACK counter 1
granted ACK counter 2
granted ACK counter 3
granted ACK counter 4
Every time the PowerPC performs a write access, whose address is higher or equal
than the performance monitor 2 address low, and lower than the performance monitor
2 address high, this counter is incremented¹.
Every time the DRAMC grants a request for channel 0, this counter is incremented¹.
Every time the DRAMC grants a request for channel 1, this counter is incremented¹.
Every time the DRAMC grants a request for channel 2, this counter is incremented¹.
Every time the DRAMC grants a request for channel 3, this counter is incremented¹.
Every time the DRAMC grants a request for channel 4, this counter is incremented¹.
cumulative wait counter 0
Every time there is a request pending to the DRAMC for channel 0, and its not granted
in the current cycle, this counter is incremented¹.
cumulative wait counter 1
Every time there is a request pending to the DRAMC for channel 1, and its not granted
in the current cycle, this counter is incremented¹.
cumulative wait counter 2
Every time there is a request pending to the DRAMC for channel 2, and its not granted
in the current cycle, this counter is incremented¹.
cumulative wait counter 3
Every time there is a request pending to the DRAMC for channel 3, and its not granted
in the current cycle, this counter is incremented¹.
cumulative wait counter 4
summed priority counter 0
summed priority counter 1
summed priority counter 2
summed priority counter 3
(SPRIOCTR3)
summed priority counter 4
(SPRIOCTR4)
Every time there is a request pending to the DRAMC for channel 4, and its not granted
in the current cycle, this counter is incremented¹.
Every time a request is granted by the DRAMC for channel 0, a priority code² is added
to this counter¹.
Every time a request is granted by the DRAMC for channel 1, a priority code² is added
to this counter¹.
Every time a request is granted by the DRAMC for channel 2, a priority code² is added
to this counter¹.
Every time a request is granted by the DRAMC for channel 3, a priority code² is added
to this counter¹. This counter shares a register location with granted ACK counters 3
and 4 and cumulative wait counter 0.
Every time a request is granted by the DRAMC for channel 4, a priority code² is added
to this counter¹. This counter shares a register location with cumulative wait counters
1, 2 and 3.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
14-21