PXD20RM Datasheet, PDF (1016/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-44. TCD settings (master node, RX mode) (continued)
TCD field
NBYTES[31:0]
SADDR[31:0]
SOFF[15:0]
SSIZE[2:0]
SLAST[31:0]
DADDR[31:0]
DOFF[15:0]
DSIZE[2:0]
DLAST_SGA[31:0]
INT_MAJ
D_REQ
START
Value
[4] + 4/8 = N
BIDR address
4
2
–N
RAM address
4
2
–N
0/1
1
0
Description
Data buffer is stuffed with dummy bytes if the length is not
word aligned.
BIDR + BDRL + BDRM
—
Word increment
Word transfer
—
—
Word increment
Word transfer
No scatter/gather processing
Interrupt disabled/enabled
Only on the last TCD of the chain.
No software request
27.11.3 Slave node, TX mode
On a slave node in TX mode, the DMA interface requires a DMA TX channel for each ID filter
programmed in TX mode. In case a single DMA TX channel is available, a single ID field filter must be
programmed in TX mode. Each TCD controls a single frame, except for the extended frames (multiple
TCDs). The memory map associated to the TCD chain (RAM area and LINFlexD registers) is shown in
Figure 27-47.
27-60
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor