PXD20RM Datasheet, PDF (207/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 8-3. MC_CGM memory map (continued)
Address
Name
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0xC3FE CGM_AC3_D R
_039C C0
W
000
DIV0
00000000
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
0xC3FE CGM_AC4_S R 0 0 0 0
_03A0 C
W
SELCTL
00000000
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
0xC3FE CGM_AC4_D R
_03A4 C0
W
000
DIV0
00000000
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
0xC3FE
_03A8
…
0xC3FE
_3FFC
reserved
8.3.3.1 Register Descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered
according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address
0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373.
8.3.3.1.1 VIU2 multiplex select register (CGM_VIU_MUX)
Address: 0xC3FE_0340
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _VIU 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W ^SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0 0
0
AUTO_DIV2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-3. VIU2 multiplex select register (CGM_VIU_MUX)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-11