PXD20RM Datasheet, PDF (817/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

21.3 Memory map and registers
This section provides a detailed description of all flash memory and PFLASH2P registers.
21.3.1 Module Memory Map
The flash memory map is shown in Table 21-1. The addresses are given as an offset to the flash memory
base address.
The flash register memory map is shown in Table 21-2. There are no program-visible registers that
physically reside inside the flash. The flash receives control and configuration information from the flash
array controller to determine operating configurations. These are part of the flash array controller’s
configuration registers mapped into the IPS address space but are described herein. These registers should
only be referenced with 32-bit accesses. Also included in the flash memory map is a block that contains
non-volatile configuration values that are used to initialize certain flash and SoC features. This is known
as the Shadow flash and is included in this table for completeness but is not intended for storage of user
program or data.
Table 21-1. Flash Memory Map
Offset from FLASH_BASE
(0x0000_0000)
Use
0x0000_0000
0x0000_4000
0x0000_8000
0x0000_C000
0x0001_0000
0x0001_4000
0x0001_8000
0x0001_C000
0x0002_0000
0x0003_0000
0x0004_0000
0x0006_0000
0x0008_0000
0x000C_0000
0x0010_0000
0x0014_0000
0x0018_0000
0x001C_0000
0x0020_0000–0x00FF_BFFF
Low-address space
Mid-address space
High-address space
Reserved
Block¹
L0
L1
L2
L3
L4
L5
L6
L7
L8
L9
M0
M1
H0
H1
H2
H3
H4
H5
Partition
1
2
3
4
5
6
7
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-5