PXD20RM Datasheet, PDF (1377/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• FIFO underrun and transfer complete interrupts
39.7.8.2 Clock Choices
When no dedicated clock sources are provided for the sample rate of 44.1/22.05/11.025 kHz and
48/24/8KHz on this device, the solution below is used to minimize the sample rate variation.
• SGM prescalers will be programmed in such a way, that its sampling frequency is always slightly
higher than I2S
• Once enabled, I2S will keep asking for data from SGM. I2S maintains the actual sample rate
control, so its prescaler should be accurately programmed
• An Underrun (I2S needing data, but SGM not able to process that fast) will never happen
39.7.8.3 I2S Block Diagram
I2S Bus
SGM IPS
Logic
SGM logic
SGM Clocking logic
I2S FIFO
Configuration
Signals for I2S
System Clk
side band signal
I2S Master Logic
I2S Clock Prescaler
I2S Master
Interface
Figure 39-47. I2S block diagram
39.7.8.4 Supported Protocol modes
This section describes the I2S modes supported by the interface. Configuration of the protocol modes are
done using the control and output data format registers (Section 39.6.2.30, I2S Control Register (I2SCTL)
and Section 39.6.2.31, I2S Output Data Format Control Register (I2SDFC)).
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
39-53