PXD20RM Datasheet, PDF (1505/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Offset: 0x000
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CPS
W
000000
FRZ TEN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 45-2. STM Control Register (STM_CR)
Table 45-2. STM_CR field descriptions
Field
Description
16:23
CPS
30
FRZ
31
TEN
Counter Prescaler. Selects the clock divide value for the prescaler (1 - 256).
0x00 Divide system clock by 1
0x01 Divide system clock by 2
...
0xFF Divide system clock by 256
Freeze. Allows the timer counter to be stopped when the device enters debug mode.
0 STM counter continues to run in debug mode.
1 STM counter is stopped in debug mode.
Timer Counter Enabled.
0 Counter is disabled.
1 Counter is enabled.
45.3.2.2 STM Count Register (STM_CNT)
The STM Count Register (STM_CNT) holds the timer count value.
Offset: 0x004
Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 45-3. STM Count Register (STM_CNT)
Table 45-3. STM_CNT field descriptions
Field
Description
0:31 Timer count value used as the time base for all channels. When enabled, the counter increments at the
CNT rate of the system clock divided by the prescale value.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
45-3