PXD20RM Datasheet, PDF (1225/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Refer to Section 35.5.3.1, Issuing SFM Commands, for further details about the triggering of IP
Commands.
Address: QSPI_BASE +
0x104
Write: ICO: QSPI_SFMSR[IP_ACC] = 0
IC: QSPI_SFMSR[IP_ACC] = 0
and QSPI_SFMSR[AHB_ACC] = 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
ICO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ICO
IC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 35-6. Instruction Code Register (QSPI_ICR)
Table 35-12. QSPI_ICR Field Descriptions
Field
ICO
IC
Description
Instruction Code Options, additional parameters for the IC instruction described below. Meaning of
the individual bits vary for each instruction code and vendor, detailed description in Table 35-41.
Write access: Instruction Code of the SFM command to be executed next.
Read access: Instruction Code of the last SFM command successfully written.
Upon writing this byte a new command sequence is started to the external serial flash device.
35.4.4.6 Sampling Register (QSPI_SMPR)
The Sampling Register allows configuration of the scheme how the incoming data from an external serial
flash device are sampled in the QuadSPI module.
Address: QSPI_BASE + 0x108
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 35-7. Sampling Register (QSPI_SMPR)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-15