PXD20RM Datasheet, PDF (1496/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Debug Status Port enable and selection
• Bus and peripheral abort enable/disable
44.1.3 Modes of operation
The SSCM operates identically in all system modes.
44.2 Memory map and register description
This section provides a detailed description of all memory-mapped registers in the SSCM.
44.2.1 Memory map
Table 44-1 shows the memory map for the SSCM. Note that all addresses are offsets; the absolute address
may be calculated by adding the specified offset to the base address of the SSCM.
Table 44-1. SSCM memory map
Address
Base + 0x0000
Base + 0x0002
Base + 0x0004
Base + 0x0006
Base + 0x0008
Base + 0x000A
Base + 0x000C
Base + 0x0010
Register
System Status (STATUS)
System Memory Configuration (MEMCONFIG)
Reserved
Error Configuration (ERROR)
Debug Status Port (DEBUGPORT)
Reserved
Password Comparison Register High Word
Password Comparison Register Low Word
Location
on page 44-2
on page 44-3
on page 44-4
on page 44-5
on page 44-6
on page 44-6
All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned
to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the
STATUS register is accessible by a 16-bit READ/WRITE to address ‘Base + 0x0002’, but performing a
16-bit access to ‘Base + 0x0003’ is illegal.
44.2.2 Register description
The following memory-mapped registers are available in the SSCM. Those bits that are shaded out are
reserved for future use. To optimize future compatibility, these bits should be masked out during any
read/write operations to avoid conflict with future revisions.
44.2.2.1 System Status Register (STATUS)
The System Status register is a read-only register that reflects the current state of the system.
44-2
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor