PXD20RM Datasheet, PDF (1022/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-48. TCD settings (slave node, RX mode) (continued)
TCD Field
Value
Description
NBYTES[31:0]
[4] + 4/8 = N
Data buffer is stuffed with dummy bytes if the length
is not word aligned.
BIDR + BDRL + BDRM
SADDR[31:0]
BDRL address
SOFF[15:0]
4
Word increment
SSIZE[2:0]
2
Word transfer
SLAST[31:0]
–N
DADDR[31:0]
RAM address
DOFF[15:0]
4
Word increment
DSIZE[2:0]
2
Word transfer
DLAST_SGA[31:0] –N
No scatter/gather processing
INT_MAJ
0/1
Interrupt disabled/enabled
D_REQ
1
Only on the last TCD of the chain.
START
0
No software request
27.11.5 UART node, TX mode
In UART TX mode, the DMA interface requires a DMA TX channel. A single TCD can control the
transmission of an entire Tx buffer. The memory map associated with the TCD chain (RAM area and
LINFlexD registers) is shown in Figure 27-51.
RAM area
LINFlex2 regs
DMA transfer (8/16 bits data format)
TCD (n)
BDRL (M bytes)
BDRL (M half-words)
BDRL
(4 bytes FIFO mode)
BDRL
(2 half-words FIFO mode)
Buffer (n)
TCD (n+1)
BDRL (M bytes)
BDRL (M half-words)
BDRL
(4 bytes FIFO mode)
BDRL
(2 half-words FIFO mode)
Buffer (n+1)
1 DMA TX channel (TCD single and/or linked chain)
Figure 27-51. TCD chain memory map (UART node, TX mode)
The UART TX buffer must be configured in FIFO mode in order to:
• Allow the transfer of large data buffer by a single TCD
27-66
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor