PXD20RM Datasheet, PDF (1251/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Note that there is a time where it is illegal to issue a new SFM Command. This time starts, due to the
internal processing pipeline, 2 clock cycles prior to raising the request to enter the Module Disable Mode.
This time ends with leaving the Module Disable Mode.
35.5.4.3 Leaving Power Saving Modes
In the Stop Mode and the Module Disable Mode the clocks to the QuadSPI module are switched off by
external circuitry. Note that after the QuadSPI module has left these power saving modes and has returned
to Normal Mode the execution of the first SFM Command is deferred until the clock to drive that part of
the module related to the serial flash device is available. Depending from the point in time when the first
SFM Command is triggered the actual execution of that command will start with a slight delay w.r.t. the
re-enabling of the clock signal.
35.5.4.4 Slave Bus Signal Gating
The QuadSPI’s module enable signal is used to gate slave bus signals such as address, byte enable,
read/write and data. This prevents toggling slave bus signals from propagating through parts of the
QuadSPI’s combinational logic and consuming power unless it is a QuadSPI access. The module enable
signal can also be used to gate the clock (ipg_clk_s) to the memory-mapped logic.
35.6 Initialization/Application Information
35.6.1 Power Up and Reset
Note that the serial flash devices connected to the QuadSPI module may require special voltage
characteristics of their inputs during power up or reset. It is within the responsibility of the application to
ensure this.
35.6.2 Available Status/Flag Information
This paragraph gives an overview over the different status and flag information available and their
interdependencies for different use cases. Related registers are QSPI_SFMSR and QSPI_SFMFR. Refer
to the related descriptions how to set up the QuadSPI module appropriately.
35.6.2.1 IP Commands
Refer to Section 35.4.4.5, Instruction Code Register (QSPI_ICR), for additional details not explicitly
covered in this paragraph.
35.6.2.1.1 IP Commands - Normal Operation
Writing the QSPI_ICR[IC] field triggers the execution of a new IP Command. Given that this is a legal
command the QSPI_SFMSR[IPACC] and the QSPI_SFMSR[BUSY] bits are asserted simultaneously
immediately after the execution is started.
When the instruction on the serial flash device has been finished these bits are de-asserted and the
QSPI_SFMFR[TFF] flag is set.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-41