PXD20RM Datasheet, PDF (1281/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• RTC counter enable
• RTC interrupt enable
• RTC clock source select
• RTC compare value
• API enable
• API interrupt enable
• API compare value
Offset RTC_BASE + 0x0004
0
123
4
R CNT RTCI FRZ ROVR
EN
W
E EN EN
POR 0
000
0
Access: User read/write
5 6 7 8 9 10 11 12 13 14 15
RTCVAL[
0 0000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R API APIIE CLKSEL DIV51 DIV3
EN
W
2EN 2EN
APIVAL
POR 0
000
0
0 0000000000
Figure 36-4. RTC Control Register (RTCC)
Table 36-3. RTCC field descriptions
Field
CNTEN
RTCIE
FRZEN
Description
Counter Enable
The CNTEN bit enables the RTC counter. Making CNTEN bit 1’b0 has the effect of
asynchronously resetting (synchronous reset negation) all the RTC logic. This allows for the
RTC configuration and clock source selection to be updated without causing synchronization
issues.
1 Counter enabled
0 Counter disabled
RTC Interrupt Enable
The RTCIE bit enables interrupts requests to the system if RTCF is asserted.
1 RTC interrupts enabled
0 RTC interrupts disabled
Freeze Enable Bit
The counter freezes on entering the debug mode (as the ipg_debug is detected active) on the
last valid count value if the FRZEN bit is set. After coming of the debug mode counter starts from
the frozen value.
0 Counter does not freeze in debug mode.
1 Counter freezes in debug mode.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
36-5