PXD20RM Datasheet, PDF (415/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

11.4.4.1 Blending priority of layers
The 16 layers available in the DCU3 are each fixed in priority order, with layer 0 being the highest priority,
layer 1 being the second highest priority, and so on until layer 15, which is the lowest priority. The priority
is used by the DCU3 to define how to blend individual pixels within the layers. For example, if layer 0 is
defined as not being blended with other layers and a pixel on layer 0 overlaps a pixel on layer 1 then the
pixel on layer 0 will be visible on the panel unchanged by the pixel on layer 1. However, if layer 0 is
defined as being partially transparent, then the DCU3 will blend the overlapping pixel such that the result
is a combination of the pixel on layer 0 and the pixel on layer 1. It is possible to blend up to four layers at
each pixel position.
As there is a maximum number of layers that can blended together, then any pixel on a layer that is lower
than the threshold priority will not be included in any blend. If a pixel is on a layer that has the lowest
priority in any blending scheme, then the blending settings for that pixel are ignored and the pixel is treated
as a background pixel. This means that a lower priority layer may have some pixels completely obscured
by those on higher priority layers on one part of the panel, and some other pixels visible or blended on
other parts of the panel.
Figure 11-64 shows how the pixel blend takes place inside the DCU3. The priority of the layers determines
at which stage of the blend the pixel enters. Any pixels lower than the threshold priority are ignored and,
as can be seen, the blend settings for the lowest priority pixel is also ignored. The maximum number of
pixels in the blend is configured by the BLEND_ITER bit field in the DCU_MODE register. As can be
seen in the figure, the blending process is iterative so that four-pixel blending takes more DCU3 clock
cycles than three-pixel blending, and three-pixel blending takes more DCU3 clock cycles than two-pixel
blending.
Highest priority pixel
Blend3
Four-plane blending
Next higher priority pixel
Blend2
Three-plane blending result
Higher priority pixel
Lowest priority pixel
Blend1
Two-plane Blending Result
Note: All blend stages use the blending settings
defined for the upper pixel.
Figure 11-64. Pixel blending stack
This priority concept is illustrated in Figure 11-65 and Figure 11-66. In this case, there are five layers
enabled, and each contains a graphic that is a solid rectangular block of a single color. The size and shape
of each layer is different. The background color of the panel is set to grey and layers have been placed such
that they overlap each other.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-81