PXD20RM Datasheet, PDF (285/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

9.6.2.5 Error Response Terminated Accesses
A master access will be responded to with an error if the hsel input of the XBAR is asserted and the transfer
type is non IDLE and the access decodes to a location not occupied by a slave port. This is the only time
the XBAR will respond with an error response. All other error responses received by the master are the
result of error responses on the slave ports being passed through the XBAR.
9.6.3 Slave Ports
The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are
actively making requests. In order to do this the XBAR must not insert any bubbles onto the slave bus
unless absolutely necessary.
There is only one instance when the XBAR will force a bubble onto the slave bus when a master is actively
making a request. This occurs when a higher priority master has control of the slave port and is running
single clock (zero wait state) accesses while a lower priority master is stalled waiting for control of the
slave port. When the higher priority master either leaves the slave port or runs an IDLE cycle to the slave
port the XBAR will take control of the slave bus and run a single IDLE cycle before giving the slave port
to the lower priority master that was waiting for control of the slave port.
The only other times the XBAR will have control of the slave port is when the XBAR is halting or when
no masters are making access requests to the slave port and the XBAR is forced to either park the slave
port on a specific master or put the slave port into low power park mode.
In most instances when the XBAR has control of the slave port it will indicate IDLE for the transfer type,
negate all control signals and indicate ownership of the slave bus via the hmaster encoding of 4’b0000.
One exception to this rule is when a master running locked cycles has left the slave port but continues to
run locked cycles. In this case the XBAR will control the slave port and will indicate IDLE for the transfer
type but it will not affect any other signals.
NOTE
When a master runs a locked cycle through the XBAR, the master will be
guaranteed ownership of all slave ports it accesses while running locked
cycles for one cycle beyond when the master finishes running locked cycles.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-27