PXD20RM Datasheet, PDF (718/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

18.6.2.8 eMIOS200 UC Control Register (CCR[n])
The Control register gathers bits reflecting the status of the UC input/output signals and the overflow
condition of the internal counter, as well as several read/write control bits.
address: UC[n] base address + 0x0C
0
1
R _{FREN ODIS}
W
RESET: ₀
0
2
3
ODISSL
0
0
4
5
6
7
8
UCPRE UCPR DMA 0
EN
0
0
0
0
0
9
10 11 12 13 14 15
IF
FCK FEN 0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R₀
W
0
0
0
0
FORC FORC
MA MB
BSL
EDSE EDPO
L
L
MODE
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or reserved
Figure 18-11. eMIOS200 UC Control Register (CCR[n])
Table 18-12. CCR[n] field descriptions
Field
FREN
ODIS
ODISSL
UCPRE
Description
Freeze Enable bit
The FREN bit, if set and validated by MCR[FRZ], allows the channel to enter freeze state, freezing
all registers values when in debug mode and allowing the MCU to perform debug functions.
1 = Freeze UC registers values
0 = Normal operation
Output Disable bit
The ODIS bit allows disabling the output pin when running any of the output modes with the exception
of GPIO mode.
1 = If the flag is set in the channel selected by the ODISSL bits, the output pin goes to EDPOL for
OPWFMB and OPWMB modes and to the complement of EDPOL for other output modes, but the
Unified Channel continues to operate normally, i.e., it continues to produce FLAG and matches.
When the selected Output Disable Input signal is negated, the output pin operates normally
0 = The output pin operates normally
Output Disable select bits
The ODISSL[0:1] bits select one of the four channels which can be used as the output disable signal,
as shown in Table 18-13.
Prescaler bits
The UCPRE[0:1] bits select the clock divider value for the internal prescaler of Unified Channel, as
shown in Table 18-14.
18-16
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor