PXD20RM Datasheet, PDF (284/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

9.6.1 Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate in parallel with multiple slaves. In order to maximize data throughput it is essential to keep
arbitration delays to a minimum.
This section examines data throughput from the point of view of masters and slaves, detailing when the
XBAR will stall the masters or insert bubbles on the slave side.
9.6.2 Master Ports
Master accesses will receive one of four responses from the XBAR. They will either be ignored,
terminated, taken, stalled or responded to with an error.
9.6.2.1 Ignored Accesses
A master access will be ignored if the hsel input of the XBAR is not asserted. The XBAR will respond to
IDLE transfers when the hsel input is asserted but will not allow the access to pass through the XBAR.
9.6.2.2 Terminated Accesses
A master access will be terminated if the hsel input of the XBAR is asserted and the transfer type is IDLE.
The XBAR will terminated the access and it will not be allowed to pass through the XBAR.
9.6.2.3 Taken Accesses
A master access will be taken if the hsel input of the XBAR is asserted and the transfer type is non IDLE
and the slave port to which the access decodes is either currently servicing the master or is parked on the
master. In this case the XBAR will be completely transparent and the master’s access will be immediately
seen on the slave bus and no arbitration delays will be incurred.
9.6.2.4 Stalled Accesses
A master access will be stalled if the hsel input of the XBAR is asserted and the transfer type is non IDLE
and the access decodes to a slave port that is busy serving another master, parked on another master or is
in low power park mode. The XBAR will indicate to the master that the address phase of the access has
been taken but will then queue the access to the appropriate slave port to enter into arbitration for access
to that slave port.
If the slave port is currently parked on another master or is in low power park mode and no other master
is requesting access to the slave port then only one clock of arbitration will be incurred. If the slave port is
currently serving another master of a lower priority and the master has a higher priority than all other
requesting masters then the master will gain control over the slave port as soon as the data phase of the
current access is completed (burst and locked transfers excluded). If the slave port is currently servicing
another master of a higher priority then the master will gain control of the slave port once the other master
releases control of the slave port if no other higher priority master is also waiting for the slave port.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor