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PXD20RM Datasheet, PDF (135/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller
• The SWT is started on PHASE1 exit and counts unconditionally during PHASE2 to monitor flash
boot sequence. SWT is held in reset during PHASE3 but can start again at PHASE3 exit depending
on the value of the shadow flash configuration bit NVUSR0[WATCHDOG_EN].
4.2.3 Modes of operation
When enabled, the SWT is always active in all modes except STANDBY when it is always disabled and
STOP when it may be disabled by the SWT_CR[STP] bit. If the STP bit is set, the counter is stopped in
STOP mode, otherwise it continues to run. On exit from STOP mode, the SWT will continue from the state
it was before entering STOP mode.
To simplify software development it is possible to temporarily suspend the SWT counter while the MCU
is stopped by a debugger. While the MCU is running the SWT counter runs normally. This feature is
enabled by setting the SWT_CR[FRZ] bit and is only available when the CPU has debug mode active (see
the CPU reference manual for more information on debug mode and support).
Software watchdog is not available in STANDBY mode. As soon as out of STANDBY mode, the SWT
behaves as in a usual “out of reset” situation.
Figure 4-12 shows the operation timing diagram of the SWT. Table 4-5describes the SWT operation after
reset.
MC_ME mode
RESET
DRUN
Reset phases
PHASE0 PHASE1
PHASE2 PHASE3
SWT status
Disabled
Enabled
(see note 1) Disabled
IDLE
Enabled if WEN = 1
SWT_CR[WEN]
See note 2
Notes:
1) The SWT is started on PHASE1 exit and counts unconditionally during PHASE2 to monitor the flash memory boot sequence.
2) Value copied from configuration bit NVUSR0[WATCHDOG_EN] in the shadow flash memory (software can modify it later)
SWT_CR
[WEN]
0
Figure 4-12. SWT operation timing diagram
Table 4-5. SWT operation after reset
MCU mode
—
CPU debug
active
No
SWT_CR
[FRZ]
0 or 1
SWT_CR
[STP]
0 or 1
SWT operation
Off
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
4-11