PXD20RM Datasheet, PDF (262/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

When a slave bus is being IDLEd by the XBAR it can park the slave port on the master port indicated by
the PARK bits in the SGPCR (Slave General Purpose Control Register). This can be done in an attempt to
save the initial clock of arbitration delay that would otherwise be seen if the master had to arbitrate to gain
control of the slave port. The slave port can also be put into low power park mode in attempt to save power.
9.3 XBAR registers
This section provides information on XBAR registers.
9.3.1 Register summary
There are four registers that reside in each slave port of the XBAR and one register that resides in each
master port of the XBAR. These registers are IP bus compliant registers. Read and write transfers both
require two IP bus clock cycles. The registers can only be read from and written to in supervisor mode.
Additionally, these registers can only be read from or written to by 32-bit accesses.
The registers are fully decoded and an error response is returned if an unimplemented location is accessed
within the XBAR.
The slave registers also feature a bit, which when written with a 1, will prevent the registers from being
written to again. The registers will still be readable, but future write attempts will have no effect on the
registers and will be terminated with an error response.
The memory map for the XBAR program-visible registers is shown in Table 9-2. Table 9-3 shows the
XBAR register summary.
Table 9-2. XBAR registers
Address offset
0x000
0x004
0x010
0x014
0x100
0x104
0x110
0x114
0x200
0x204
0x210
0x214
0x300
0x304
0x310
0x314
0x400
0x404
0x410
Use
Master Priority Register for Slave port 0 (MPR0)
Reserved
General Purpose Control Register for Slave port 0 (SGPCR0)
Reserved
Master Priority Register for Slave port 1 (MPR1)
Reserved
General Purpose Control Register for Slave port 1 (SGPCR1)
Reserved
Master Priority Register for Slave port 2 (MPR2)
Reserved
General Purpose Control Register for Slave port 2 (SGPCR2)
Reserved
Master Priority Register for Slave port 3 (MPR3)
Reserved
General Purpose Control Register for Slave port 3 (SGPCR3)
Reserved
Master Priority Register for Slave port 4 (MPR4)
Reserved
General Purpose Control Register for Slave port 4 (SGPCR4)
Location
on page 9-6
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on page 9-9
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on page 9-6
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on page 9-9
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on page 9-6
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on page 9-9
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on page 9-6
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on page 9-9
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on page 9-6
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on page 9-9
PXD20 Microcontroller Reference Manual, Rev. 1
9-4
Freescale Semiconductor
Preliminary—Subject to Change Without Notice