PXD20RM Datasheet, PDF (1549/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Chapter 47
Video Input Unit (VIU2)
47.1 Introduction
The VIU2 is an enhanced version of the original Video-In (VIU) block, with new features added including
Down-scaling, Brightness and Contrast adjustment, and YUV 4:2:2 output.
Figure 47-1 shows a block diagram of the VIU2.
Data[9:0]
PAD
Pixclock
PAD
IPG_CLK domain
Synch
ronizer
1
ITU
Decoder
2
HScale
VScale
3
B/C
Adjust
4
yuv2rgb
5
Output
Formatter
6
FIFO(256x64bit) ^IRQ
DMA engine
IPM bus
7
Registers
IPS_CLK domain
Figure 47-1. VIU2 block diagram
IPS bus
47.1.1 Features
• Support from QVGA to XVGA 8-bit/10-bit ITU656 video input¹
• Up to 1/8 video down-scaling
• Support different scaling ratio on horizontal and vertical direction
• Brightness/contrast adjust
• YUV to RGB 888/565 conversion
• Simple de-interlace function (weaving) for interlaced/or pseudo interlaced video input
• Internal DMA engine for transfering data from FIFO to system memory
47.2 Memory map and register definition
47.2.1 Memory map
Table 47-1. VIU2 memory map
Address offset
Register
0x00
0x04
Status And Configuration Register (SCR)
Luminance Coefficients For Red, Green And Blue Matrix (LUMA_COMP)
Access
RW
RW
Location
on page 47-5
on page 47-7
1. When down scaling and/or B/C adjust is enabled, the two LSB’s of the 10-bit input are ignored.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
47-1