PXD20RM Datasheet, PDF (1173/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Offset: 0x042
Access: User read/write
Field Reset
Description
31–12
11–0
0x0 Page Table Base address (PT_BASE[31:12]) aligned to a 4kB page boundary (PT_BASE[11:0]=0).
0x0 Alignment, zeroed.
31.5.4 MH_MMU_PAGE_FAULT
Offset: 0x043
Access: User read
Field
31–12
11
10
9
8
7
6–4
3–2
1
0
Reset
Description
0x0 VA[31:12] of lookup that caused the page fault
0x0 Page table entry not valid for write operation
0x0 Page table entry not valid for read operation
0x0 Client VA not in VA range
0x0 Client PA not in MPU range
0x0 Padding bit
0x0 AXI ID of lookup that caused the page fault
0x0 Reports programmed client behavior bits at the time of page fault. See Table 31-17.
0x0 Operation Type, 0 = read, 1 = write
0x0 Page fault occured
31.5.5 MH_MMU_TRAN_ERROR
Offset: 0x044
Access: User read/write
Field
31–5
14–0
Reset
Description
0x0
Address location (TRAN_ERROR[31:5]) used for dummy reads or writes in the event of a page fault,
aligned on a 32-bit boundary (TRAN_ERROR[4:0]=0).
0x0 Alignment, zeroed.
31.5.6 MH_MMU_INVALIDATE
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
31-41