PXD20RM Datasheet, PDF (635/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

15.3.3 Interrupts and exception handling
The e200z4d core supports an extended exception handling model with nested interrupt capability and
extensive interrupt vector programmability. In general, interrupt processing begins with an exception that
occurs due to external conditions, errors, or program execution problems. When an exception occurs, the
processor checks whether interrupt processing is enabled for that particular exception. If enabled, the
interrupt causes the state of the processor to be saved in the appropriate registers and begins execution of
the handler located at the associated vector address for that particular exception.
Once the handler is executing, the implementation may need to check bits in the exception syndrome
register (ESR), the machine check syndrome register (MCSR), or the signal processing and embedded
floating-point status and control register (SPEFSCR) to verify the specific cause of the exception and take
appropriate action.
The core complex supports the interrupts described in Table 15-1.
Table 15-1. Interrupt registers
Register
Description
SRR0
SRR1
CSRR0
CSRR1
DSRR0
DSRR1
MCSRR0
MCSRR1
MCSR
Noncritical Interrupt Registers
Save/restore register 0—On noncritical interrupts, stores either the address of the instruction causing
the exception or the address of the instruction that executes after the rfi instruction.
Save/restore register 1—Saves machine state on noncritical interrupts and restores machine state
after an rfi instruction is executed.
Critical Interrupt Registers
Critical save/restore register 0—On critical interrupts, stores either the address of the instruction
causing the exception or the address of the instruction that executes after the rfci instruction.
Critical save/restore register 1—Saves machine state on critical interrupts and restores machine state
after an rfci instruction is executed.
Debug Interrupt Registers
Debug save/restore register 0—On debug interrupts, stores either the address of the instruction
causing the exception or the address of the instruction that executes after the rfdi instruction.
Debug save/restore register 1—Saves machine state on debug interrupts and restores machine state
after an rfdi instruction is executed.
Machine Check Interrupts
Machine check save/restore register 0—On machine check interrupts, stores either the address of the
instruction causing the exception or the address of the instruction that executes after the rfmci
instruction.
Machine check save/restore register 1—Saves machine state on machine check interrupts and
restores those values when an rfmci instruction is executed
Syndrome Registers
Machine check syndrome register—Saves machine check syndrome information on machine check
interrupts.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
15-9