PXD20RM Datasheet, PDF (622/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

TerCount condition _R
Event
+1
en
1_{All counters in this table are double-buffered. Figure at the left gives the}
details. There are always 2 registers associated with every counter. The first
register is the “counter”. It counts the events mentioned in the table. When
the trigger condition occurs- the time event counter reaching terminal count
Readable
Value
-, the “counter” register is transferred to the “buffer” register, and the
“counter” register is cleared. When accessing the register, its always the
"counter"
register
"buffer"
register
buffer register value that is returned.
2 _{The priority code added may or may not be the same as the priority code the request used on the DRAMC. The codes will be}
equal if the LUT sel field for the channel is the same in registers prioman_config and perfmon_config. If the LUT sel fields differ,
the field in prioman_config is used to calculate the channel priority code on the DRAM, and the field in perfmon_config is used
to calculate the priority code added to this register.
The possibility to use unequal LUT sel fields, makes it possible to use the “main” look-up tables for DRAM priority programming,
and the “alternate” look-up tables for performance monitoring. Making the look-up tables independent, opens a wide possibility
in what can be monitored.
14.5 Functional description
The priority manager calculates the outgoing priority for all 5 channels of DRAMC. The priority of any
channel at a given time, is a function of the request granting history of the DRAMC. A granted request is
called an ACK, so this schema is called an ACK-based schema, because the priority is determined by the
history of which channels have been ACK-ed in the past and when.
The block diagram in Figure 14-2 makes this dependency clear: Priority manager determines priority on
the basis of the outstanding requests, and the requests granted (the ACK’s) by the DRAMC.
The priority manager calculates the priorities in a dynamic way. This means, a priority is never constant,
but changes over time, even when the request is not serviced. As a request ages while its not being
serviced, its priority will escalate to higher level, and as the level increases, it will eventually be serviced.
The DRAMC has a built-in preference to offer repeat for any incoming read request. The repeat goes on
as long as the requesting channel keeps requesting, and its priority is greater than 0. When the outgoing
priority for any channel is 0, the DRAMC will no longer service or repeat the request. This feature allows
the priority manager to control the maximum repeat count for any incoming channel.
14.5.1 Description of operation — overview
Priority calculation for all channels is independent. So, there is no direct cross-dependency of the priority
of one channel on the priority of another channel. The algorithm looks at the last N arbitration cycles on
the bus. N is a programmable number, set by fields ack_count in register prio_man, described in
Figure 14-3. For the last N arbitration cycles, the number of times the own channel won the bus, is summed
up, and saturated to a maximum of 15. This number of 0 to 15 is then input into the applicable look-up
table, and the value for the particular number, is the priority code going to the DRAMC. If e.g. N is set to
16, and the own channel was granted the bus 4 times in the last 16 bus grant, the index into the look-up
table is 4, and the field prio4 of the relevant look-up table will be the priority going to the DRAMC.
There are 2 look-up tables for every channel. The “main” look-up table, and the “alternate” look-up table.
The algorithm may switch between both, depending on some settings.
• The “default” look-up table is the “main.” However, the “alternate” will be used if
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor