PXD20RM Datasheet, PDF (266/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 9-5. Master Priority Register Descriptions (continued)
Name
MSTR_4
Description
Settings
Master 4 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 4 on the associated slave port.
when accessing the slave port.
Bit 16
MSTR_3
These bits are initialized by hardware reset.
The reset value is 100
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 3 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 3 on the associated slave port.
when accessing the slave port.
Bit 20
MSTR_2
These bits are initialized by hardware reset.
The reset value is 011
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 2 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 2 on the associated slave port.
when accessing the slave port.
Bit 24
MSTR_1
These bits are initialized by hardware reset.
The reset value is 010
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 1 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 1 on the associated slave port.
when accessing the slave port.
Bit 28
MSTR_0
These bits are initialized by hardware reset.
The reset value is 001
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 0 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 0 on the associated slave port.
when accessing the slave port.
These bits are initialized by hardware reset.
The reset value is 000
111This master has the lowest priority
when accessing the slave port.
The Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once the RO
(Read Only) bit has been set in the slave General Purpose Control Register the Master Priority Register
can only be read from, attempts to write to it will have no effect on the MPR and result in an error response.
NOTE
No two available master ports may be programmed with the same priority
level. Attempts to program two or more available masters with the same
priority level will result in an error response and the MPR will not be
updated.
PXD20 Microcontroller Reference Manual, Rev. 1
9-8
Freescale Semiconductor
Preliminary—Subject to Change Without Notice