PXD20RM Datasheet, PDF (435/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

In Figure 11-82 three areas of the RAM are defined for different purposes. Area A is used by layer 1 as a
CLUT for its 4 bpp graphic. Area B is use by layer 5 as a store for its tile graphic. Area C is used by layers
2, 7, and 9 as a CLUT for their 8 bpp graphics.
CLUT/Tile RAM
16 palette entries
A
64 pixel entries
for 8 x 8 tile
B
256 palette entries
C
Figure 11-82. An example of use for the CLUT/Tile RAM
The CLUT/Tile RAM is mapped in the DCU3 16K memory space from address 0x2000 to 0x3FFF. This
gives 2048 entries, which provides up to eight full CLUTs for 8 bpp layers.
The CLUT/Tile RAM may be written at any time when the TFT LCD panel is not being driven with data.
This means that the RAM can be modified when the DCU3 is not enabled and during the vertical blanking
period.
11.4.7 Gamma correction
The gamma table allows the user to define an arbitrary transfer function at the output of each color
component. The function (Equation 11-4) is applied to each pixel after all blending is complete and before
the data is driven to the TFT LCD panel. Gamma correction is optional and can be used to adjust the color
output values to match the gamut of a particular TFT LCD panel, or to perform data inversion or data
length reduction on each component.
output_color_component = gamma_table[input_color_component]
Eqn. 11-4
The table is arranged as three separate memory blocks within the DCU3 memory map; one for each of the
three color components. Each memory block has one entry for every possible 8-bit value and the entries
are stored at 32-bit aligned addresses. This means that the upper 24 bits are not used while reading/writing
the gamma memories. See Figure 11-83 for details of the memory arrangement.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-101