PXD20RM Datasheet, PDF (1091/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 29-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions (continued)
Field
TEST
RESET
Peripheral control during TEST
0 Peripheral is frozen with clock gated
1 Peripheral is active
Peripheral control during RESET
0 Peripheral is frozen with clock gated
1 Peripheral is active
Description
29.3.2.21 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
Address 0xC3FD_C0A0 - 0xC3FD_C0BC
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0
00
0
00000000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 29-22. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
These registers configure eight different types of peripheral behavior during non-run modes.
Table 29-14. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions
Field
STANDBY
STOP
HALT
Peripheral control during STANDBY
0 Peripheral is frozen with clock gated
1 Peripheral is active
Peripheral control during STOP
0 Peripheral is frozen with clock gated
1 Peripheral is active
Peripheral control during HALT
0 Peripheral is frozen with clock gated
1 Peripheral is active
Description
29.3.2.22 Peripheral Control Registers (ME_PCTL0…143)
Address 0xC3FD_C0C0 - 0xC3FD_C14F
Access: User read, Supervisor read/write, Test read/write
0
R
0
W
Reset
0
1
DBG_F
0
2
3
4
LP_CFG
0
0
0
5
6
7
RUN_CFG
0
0
0
Figure 29-23. Peripheral Control Registers (ME_PCTL0…143)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
29-33