PXD20RM Datasheet, PDF (634/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Figure 15-3 shows the user-mode special-purpose registers.
General Registers
Timers (Read only)
Condition Register
CR
Count Register
CTR SPR 9
Link
LR
SPR 8
XER
XER
SPR 1
General-Purpose Registers
GPR0
GPR1
•
•
•
GPR31
Accumulator
Time Base
TBL
TBU
SPR 268
SPR 269
Control Registers
SPR General (Read-only)
SPRG4 SPR 260
SPRG5 SPR 261
SPRG6 SPR 262
SPRG7 SPR 263
ACC
User SPR
USPRG0 SPR 256
Cache Register
(Read-only)
Cache Configuration
L1CFG0 SPR 515
L1CFG1 SPR 516
Category Registers
SPE Status and
Control Register
SPEFSCR SPR 512
Figure 15-3. e200z4d User Mode Programmer’s Model SPRs
The GPRs are accessed through instruction operands. Access to other registers can be explicit, by using
instructions for that purpose such as the Move to Special-Purpose Register (mtspr) and Move from
Special-Purpose Register (mfspr) instructions. Access to other registers can also be implicit, as part of the
execution of an instruction. Some registers are accessed both explicitly and implicitly.
15.3.2 Instruction set
The e200z4d supports the Power ISA instruction set for 32-bit embedded implementations. This is
composed primarily of the user-level instructions defined by the user instruction set architecture (UISA).
The e200z4d does not include the Power ISA floating-point, load string, or store string instructions.
The e200z4d core implements the following architectural extensions:
• The VLE category
• The integer select category (ISEL)
• Enhanced debug and the debug notify halt instruction categories
• The machine check category
• The WAIT category
• The volatile context save/restore category
• The embedded floating-point unit, version 2
• The signal processing extension unit, version 1.1
• The cache line locking category
• The enhanced reservations category
15-8
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor