PXD20RM Datasheet, PDF (217/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 8-15. Auxiliary Clock 3 Select Control Register (CGM_AC3_SC) Field Descriptions
Field
Description
SELCTL Auxiliary Clock 3 Source Selection Control — This value selects the current source for auxiliary clock
3.
0000 system clock
0001 primary PLL
0010 secondary PLL
0011 reserved
0100 reserved
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
8.3.3.1.13 Auxiliary Clock 3 Divider Configuration Register (CGM_AC3_DC)
Address 0xC3FE_039C
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
000
DE0
W
DIV0
00000000
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-15. Auxiliary Clock 3 Divider Configuration Register (CGM_AC3_DC)
This register controls the auxiliary clock 3 divider.
Table 8-16. CGM_AC3_DC field descriptions
Field
Description
DE0
DIV0
Divider 0 Enable
0 Disable auxiliary clock 3 divider 0
1 Enable auxiliary clock 3 divider 0
Divider 0 Division Value — The resultant QuadSPI clock will have a period DIV0 + 1 times that of
auxiliary clock 3. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored
and the QuadSPI clock remains disabled.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-21