PXD20RM Datasheet, PDF (1312/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• IP bus interface for configuring the module
The crossbar interface appears in the device memory map as two FIFOs. Writes to the Rx FIFO will cause
the RLE_DEC to begin decoding operations. The RLE_DECs Finite State Machine (FSM) removes data
from the Rx FIFO, decodes it and places the output into the Tx FIFO. The decoded data appears in the Tx
FIFO and is removed from this FIFO after it is read by a crossbar master such as the CPU or eDMA. The
DMA operations require the use of two different DMA channels.
The module is configured and its status monitored using registers on the IP bus that appear as locations in
the module register memory area. This configuration includes information on the size of the image (or data
set) and the size of the individual pixels (or data elements) in the image. The RLE_DEC uses this
information to determine when an operation is complete For this reason the RLE_DEC will typically be
reconfigured for each operation since the size of each compressed image will be different.
The module can raise interrupts to indicate errors and when an operation is complete.
38.1.2 Features
The RLE_DEC supports the following features:
• Lossless decompression
• Pixel formats supported: 8bpp, 16bpp, 24bpp and 32bpp (Programmable)
• AHB mapped Rx FIFO (8x8 bytes deep) with DMA support.
• AHB mapped Tx FIFO (8x8 bytes deep) with DMA support.
• Programmable fill levels of read and write buffers for initiating burst transfers.
• Partial Image Decode feature, wherein only a portion of the decoded image is given as output. (See
Section 38.5.3, Image coordinates’ example, for details).
• Support for Stop Mode for power-saving purposes
38.1.3 RLE_DEC modes of operation
38.1.3.1 Normal Mode
In this mode, the RLE_DEC block performs the normal ‘Run Length Encoding’ Decode operation. Further
details about this mode of operation can be found in chapter 38.5.5, Normal mode.
38.1.3.2 Module Disable Mode
The Module Disable Mode is used for power management of the device containing the RLE_DEC module,
it is controlled by signals external to the RLE_DEC. The clock to the non-memory mapped logic in the
RLE_DEC can be stopped while in the Module Disable Mode. See chapter 38.5.6.1, Module Disable
Mode.
38-2
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor