PXD20RM Datasheet, PDF (1121/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 30-5. DC1 Field Descriptions
Field
Description
0
OPC¹
Output Port Mode Control.
0 Reduced-port mode configuration (2 MDO pins).
1 Full-port mode configuration (all MDO pins).
1–2
MCK_DIV[1:0]¹
MCKO Clock Divide Ratio (see note 1).
00 MCKO is 1x processor clock freq.
01 MCKO is 1/2x processor clock freq.
10 MCKO is 1/4x processor clock freq.
11 MCKO is 1/8x processor clock freq.
3–4
EOC[1:0]
EVTO Control.
00 EVTO upon occurrence of watchpoints (configured in DC2).
01 EVTO upon entry into debug mode.
10 EVTO upon timestamping event.
11 Reserved.
5
Reserved.
6
PTM
Program Trace Method.
0 Program trace uses traditional branch messages.
1 Program trace uses branch history messages.
7
WEN
Watchpoint Trace Enable.
0 Watchpoint messaging disabled.
1 Watchpoint messaging enabled.
8–23
Reserved.
24–26
OVC[2:0]
Overrun Control.
000 Generate overrun messages.
001–010 Reserved.
011 Delay processor for BTM / DTM / OTM overruns.
1XX Reserved.
27–28
EIC[1:0]
EVTI Control.
00 EVTI is used for synchronization (program trace/ data trace).
01 EVTI is used for debug request.
1X Reserved.
29–31
TM[2:0]
Trace Mode. Any or all of the TM bits may set, enabling one or more traces.
000 No trace.
1XX Program trace enabled.
X1X Data trace enabled (not supported mode)
XX1 Ownership trace enabled.
1 _{The output port mode control bit (OPC) and MCKO divide bits (MCK_DIV) are shown for clarity. These functions}
are controlled globally by the NPC port control register (PCR). These bits are writable in the PCR but have no effect.
Development control register 2 is shown in Figure 30-6 and its fields are described in Table 30-6.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-9