PXD20RM Datasheet, PDF (1442/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

42.1.3.3 Power Down Modes
When the SSD is disabled by the Mode Entry module, the analog block and the system clocks driving the
SSD blocks are disabled.
42.2 External Signal Description
Each of the four analog I/Os of the SSD block is used either as the output of a half-bridge sourcing or
sinking the current of the SM coil driven currently or - in case of acting as an input - the back EMF of the
non-driven coil with respect to an internally-generated reference voltage is supplied to the -modulator
of the analog block. The signal properties are given in Table 42-1.
Table 42-1. Signal Properties
Name
COSP
COSM
SINP
SINM
Port
COSP
COSM
SINP
SINM
Coil
Cosine
Sine
Coil Node
Plus
Minus
Plus
Minus
I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Reset
Z
Z
Z
Z
42.3 Memory Map and Register Definition
This section provides a detailed description of the registers of the SSD block. Note that all registers are
16 bits in width. There is no access on byte level.
42.3.1 Memory Map
Table 42-2 lists the registers of the SSD block.
Table 42-2. Block Memory Map
Offset
Register Name (Long)
Register Name (Short)
0x00 SSD Control and Status Register
CONTROL
0x02 SSD Interrupt Flag and Enable Register
IRQ
0x04 SSD Integrator Accumulator Register
ITGACC
0x06 SSD Down Counter Count register
DCNT
0x08 SSD Blanking Counter Load Register
BLNCNTLD
0x0A SSD Integration Counter Load Register
ITGCNTLD
0x0C
0x0E
SSD Prescaler Register
RESERVED²
PRESCALE
1 _{Note that R/W registers may contain some read-only or write-only bits.}
2 _{Read access provides 0x0000. No write allowed.}
Access¹
R/W
R/W
R
R
R/W
R/W
R/W
n/a
Location
on page 42-5
on page 42-7
on page 42-8
on page 42-8
on page 42-9
on page 42-9
on page 42-10
—
42-4
PXD20 Microcontroller Reference Manual, Rev. 1