PXD20RM Datasheet, PDF (1603/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate concurrently with multiple slaves. In order to maximize data throughput it is essential to
keep arbitration delays to a minimum. The configuration of the crossbar can have implications for the
performance of a system and particular care should be taken when assigning master priorities in a fixed
priority application. Further, by correctly parking saves on relevant masters the initial access times to the
slaves can be minimized by negating any initial arbitration penalties.
50.3.4.2 Recommended configuration
The specific settings for a given situation are application dependent and thus should be assessed by the
user. The primary flash port is fixed to the e200z4d instruction bus master to maximise execution speed
for that core however the assignment of the second flash port will depend on which other masters are
accessing the flash the most. Best performance may be obtained by prioritising the eDMA or the data bus
of the e200z4d. Similarly assignment of the system and graphics RAM ports depend on how the cores,
DCU and DCULite, and eDMA use the RAMs.
More details of the XBAR register configuration can be found in Section 9.3, XBAR registers.
50.3.5 Cache
50.3.5.1 Description
The PXD20 e200z4d provides an 8 KB Instruction, 2-way or 4-way set-associative, Harvard cache design
with a 32-byte line size. The cache is disabled by default after reset.
The cache improves system performance by providing low-latency instructions to the instruction
pipelines, which decouples processor performance from system memory performance. There are several
stages to enabling the cache. Not only does the cache itself have to be invalidated then enabled, but
memory regions upon which it can operate must be configured in the MMU to permit cache access.
50.3.5.2 Recommended configuration
The exact usage of cache is application dependent but some general guidelines for using cache to improve
performance in a typical application are listed below:
• Enable instruction cache for all internal and external memories that code is being executed from.
• Consider locking critical performance routines in cache.
The process of enabling the instruction cache involves first invalidating the cache (by setting
L1CSR1[ICINV]) then when invalidation is completed (L1CSR1[ICINV, ICABT] = 0) enabling the cache
(by setting L1CSR1[ICE]).
The L1CSR1 special purpose register is detailed below. For further details of cache configuration registers
refer to the e200z4 core reference manual.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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