PXD20RM Datasheet, PDF (1107/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

29.4.4 Protection of Mode Configuration Registers
While programming the mode configuration registers ME_<mode>_MC, the following rules must be
respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be
generated.
• The FIRC must be enabled if it is to be set as the system clock. Likewise, the FIRC cannot be
disabled whilst it is selected as the system clock.
• If the div. 4-16 MHz ext. xtal osc. clock is selected as the system clock, OSC must be on.
• If the primary PLL/2 clock is selected as the system clock, PLL and FXOSC must be on.
NOTE
Software must ensure that clock sources with dependencies other than those
mentioned above are swithced on as needed. There is no automatic
protection mechanism to check this in the MC_ME.
• Configuration “00” for the FLAON bit field is reserved.
• MVREG must be on if any of the following is active:
— CFLASH
• System clock configurations marked as ‘reserved’ may not be selected.
• Configuration “1111” for the SYSCLK bit field is allowed only for the STOP and TEST modes,
and only in this case may all system clock sources be turned off.
WARNING
If the system clock is stopped during TEST mode, the device can exit only
via a system reset.
29.4.5 Mode Transition Interrupts
The MC_ME provides interrupts for incorrectly configuring a mode, requesting an invalid mode
transition, indicating a SAFE mode transition not due to a software request, and indicating when a mode
transition has completed.
29.4.5.1 Invalid Mode Configuration Interrupt
Whenever a write operation is attempted to the ME_<mode>_MC registers violating the protection rules
mentioned in the Section 29.4.4, Protection of Mode Configuration Registers, the interrupt pending bit
I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of
ME_IM register is ‘1’.
29.4.5.2 Invalid Mode Transition Interrupt
The mode transition request is considered invalid under the following conditions:
• If the system is in the SAFE mode and the SAFE mode request from MC_RGM is active, and if
the target mode requested is other than RESET or SAFE, then this new mode request is considered
to be invalid, and the S_SEA bit of the ME_IMTS register is set.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
29-49