PXD20RM Datasheet, PDF (901/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 25-5. I-Bus Prescaler Divider Values
IBC[2:4]
000
001
010
011
100
101
110
111
scl2start
(clocks)
2
2
2
6
14
30
62
126
scl2stop
(clocks)
7
7
9
9
17
33
65
129
scl2tap
(clocks)
4
4
6
6
14
30
62
126
tap2tap
(clocks)
1
2
4
8
16
32
64
128
Table 25-6. I-Bus Tap and Prescale Values
IBC[5:7]
000
001
010
011
100
101
110
111
SCL Tap
(clocks)
5
6
7
8
9
10
12
15
SDA Tap
(clocks)
1
1
2
2
3
3
4
4
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 25-5. All subsequent tap points are separated by 2^IBC[2:4] as shown in the
tap2tap column in Table 25-5. The SCL Tap is used to generate the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to the change of state of SDA i.e. the SDA hold time.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
25-5