PXD20RM Datasheet, PDF (755/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 19-4. ECC Status (ESR) Field Descriptions (continued)
Field
RNCE
Description
RAM Non-Correctable Error
0 = No reportable non-correctable RAM error has been detected.
1 = A reportable non-correctable RAM error has been detected.
FNCE
The occurrence of a properly-enabled non-correctable RAM error generates a ECSM ECC interrupt
request. The faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT
and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
Flash Non-Correctable Error
0 = No reportable non-correctable flash error has been detected.
1 = A reportable non-correctable flash error has been detected.
The occurrence of a properly-enabled non-correctable flash error generates a ECSM ECC interrupt
request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and
FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
In the event that multiple status flags are signaled simultaneously, ECSM records the event with the R1BC
as highest priority, then F1BC, then RNCE, and finally FNCE.
19.4.2.5 ECC Error Generation Register (EEGR)
The ECC Error Generation Register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided
for two purposes:
• It provides a software-controlled mechanism for “injecting” errors into the memories during data
writes to verify the integrity of the ECC logic.
• It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash,
i.e., the ability to program the non-volatile memory with single- or double-bit errors is supported for the
same two reasons previously identified.
For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such
that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections
or double-bit noncorrectable errors that are terminated with an error response.
The enabling of these error generation modes requires the same SoC-configurable input enable signal (as
that used to enable single-bit correction reporting) be asserted.
See Figure 19-4 and Table 19-5 for the ECC Configuration Register definition.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
19-7