PXD20RM Datasheet, PDF (876/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Support for byte (8-bit), half word (16-bit), word (32-bit) and double word (64-bit) access sizes
• Full support for AMBA v6 extensions related to unaligned accesses
— Includes support for non-contiguous byte strobes on writes
• Independent data buffers (one per AHB port) for maximum system performance
— Optimized for burst transfers (read + write)
— Programmable read prefetch capabilities
• 32-bit IPS interface for access to program model
— Arbitration control giving priority to port 0 or port 1 or round robin
• Port 0 and 1 prefetch control
• Fill function for memory initialization
— Region of initialization is configurable with start and end addresses on modulo 32 byte
boundaries
— Initialization can be a load of all-zeroes or all-ones
— Status register available for the system to monitor fill operation
23.1.3 Modes of operation
The GSRAM supports all modes of operation. If a standby or low power mode is desired, it should be taken
care of off platform.
23.2 External signal description
This module has no external signals.
23.2.1 Memory map
The GSRAM programming model consists of six 32-bit registers. The programming model can only be
accessed using 32-bit (word) accesses. References using a different size are invalid and will return an error.
Other types of invalid accesses include: writes to read only registers, and accesses to reserved addresses.
Table 23-1. GSRAM memory map
Address
offset
Register
Access Reset value Location
0x0
0x4
0x8
0xC
0x10
General Registers
PRAM2P_CR - Control Register
PRAM2P_SR—Status register
PRAM2P_BEG—Beginning address for Fill register
PRAM2P_END—End Address for Fill register
PRAM2P_FIL—Fill register
R/W 0x0000_0000 on page 23-3
R 0x0000_0000 on page 23-4
R/W 0x0000_0000 on page 23-4
R/W 0x0000_0000 on page 23-5
R/W 0x0000_0000 on page 23-5
23-2
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor