PXD20RM Datasheet, PDF (658/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Channel preemption is enabled on a per channel basis by setting the ECP bit in the DCHPRIn register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. After the preempting channel has completed all of its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel will be suspended and the higher priority channel will be serviced. Nested
preemption (attempting to preempt a preempting channel) is not supported. After a preempting channel
begins execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected
for both group and channel arbitration modes.
A channel’s ability to preempt another channel can be disabled by setting the DPA bit in the DCHPRIn
register. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority
channel’s data transfer; regardless of the lower priority channel’s ECP setting. This allows for a pool of
low priority, large data moving channels to be defined. These low priority channels can be configured to
not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally
available a true, high priority channel. See Figure 16-17 and Table 16-17 for the DCHPRIn definition.
Register address: DMA_Offset + 0x100 + n
0
1
2
3
4
5
6
7
R
ECP
DPA
GRPPRI[0:1]
CHPRI[0:3]
W
RESET:
0
0
*
*
*
*
*
*
= Unimplemented,
*
= defaults to channel number (n) after reset
Figure 16-17. DMA Channel n Priority (DCHPRIn) Register
Name
ECP
DPA
GRPPRI[0:1]
CHPRI[0:3]
Table 16-17. DMA Channel n Priority (DCHPRIn) field descriptions
Description
Enable Channel Preemption
Disable Preempt Ability
Channel n Current Group Priority
Channel n Arbitration Priority
Value
0 Channel n cannot be suspended by a higher priority
channel’s service request.
1 Channel n can be temporarily suspended by the
service request of a higher priority channel.
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless
of channel priority.
Group priority assigned to this channel group when
fixed-priority arbitration is enabled. These two bits are
read only; writes are ignored.
Channel priority when fixed-priority arbitration is
enabled.
16.2.1.17 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The TCD structure was previously discussed in detail in Section 16.1.2, Features. The channel
descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel [n-1]. The
definitions of the TCD are presented as eight 32-bit values. Table 16-18 is a 32-bit view of the basic TCD
structure.
16-20
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor