PXD20RM Datasheet, PDF (233/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.4.4.3 Register Description
Address offset: 0x0000
Reset value: 0b00000000_00000000_00000000_00000000
0
1
2
3
4
5
6
7
8
reserved
Base Address: 0xC3FE_0060
9
10
11
12
13
14
15
RCTRIM
r
rw
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RCDIV
reserved
S_RC_
STDBY
reserved
r
rw
rw
r
Table 8-23. FIRC Oscillator Control Register (FIRC_CTL)
Table 8-24. FIRC Oscillator Control Register (FIRC_CTL) field descriptions
Field
Bits 0-9
Bits 10-15
Bits 16-18
Bits 19-23
Bits 24-25
Bits 26
Bits 28-31
Description
Reserved
RCTRIM[5:0]: Low power RC trimming bits
Note: Not all configurations can be used. Please refer to the device data sheet.
Reserved
RCDIV[4:0]: Low Power RC clock division factor
These bits specify the low power RC oscillator output clock division factor. The output clock is divided
by the factor LPRCDIV+1.
Reserved
S_RC_STDBY: MRC oscillator powerdown status in standby mode
This bit specifies whether MRC oscillator is powered down or not during standby mode entry. This bit
can be cleared by writing ’ 1‘.
0: MRC is not switched off during standby.
1: MRC is switched off during standby.
Reserved
Note: FIRC_CTL register is writable only in supervisor mode.
8.5 Frequency-modulated phase-locked loop (FMPLL)
8.5.1 Introduction
This section describes the features and functions of the two independent FMPLL modules (FMPLL_0 and
FMPLL_1) implemented in PXD20.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-37