PXD20RM Datasheet, PDF (614/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

14.4.2.10 Performance monitor address registers
Offsets: 0xE8 (PM1L)
0xEC (PM2L)
0xF0 (PM1H)
0xF4 (PM2H)
read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
ADDR[31:16]
W
Reset — 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ADDR [15:5]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-13. Performance Monitor Address Registers
These registers determine if a CPU (e200) access hits in the performance monitor 1 or performance
monitor 2 address space.
1. If ((e200 CPU address >= performance monitor 1 address low) &&
(e200 CPU address < performance monitor 1 address hi))
- Increment performance monitor 1 read counter on reads
- Increment performance monitor 1 write counter on writes.
2. If ((e200 CPU address >= performance monitor 2address low) &&
(e200 CPU address < performance monitor 3address hi))
- Increment performance monitor 2 read counter on reads
- Increment performance monitor 2 write counter on writes.
14.4.2.11 Counter registers
Offset: 0x100 (PM1CNTR)
read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CNTR[23:16]
W
Reset — 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CNTR[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-14. Performance Monitor 1 Read Counter (PM1CNTR)
14-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor