PXD20RM Datasheet, PDF (58/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Dynamic power management of execution units, cache and MMU
1.5.3 Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between seven master ports and
eight slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows concurrent transactions to occur from any master port to any slave port but one of
those transfers must be an instruction fetch from internal flash. If a slave port is simultaneously requested
by more than one master port, arbitration logic selects the higher priority master and grants it ownership
of the slave port. All other masters requesting that slave port are stalled until the higher priority master
completes its transactions. Requesting masters having equal priority are granted access to a slave port in
round-robin fashion, based upon the ID of the last master to be granted access.
The crossbar provides the following features:
• Seven master ports:
— e200z4d core instruction port
— e200z4d core complex load/store data port
— eDMA controller
— DCU
— DCU-Lite
— VIU
— 2D Graphics Accelerator (GFX2D)
• Seven slave ports:
— Platform Flash Controller (2 Ports)
— Platform SRAM Controller
— Graphics SRAM Controller (2 Ports)
— QuadSPI serial flash Controller and RLE Decoder
— Peripheral Bridge
• 32-bit internal address bus, 64-bit internal data bus
• Programmable Arbitration Priority
— Requesting masters can be treated with equal priority and will be granted access to a slave port
in round-robin fashion, based upon the ID of the last master to be granted access or a priority
order can be assigned by software at application run time
• Temporary dynamic priority elevation of masters
1.5.4 Enhanced Direct Memory Access (eDMA)
The eDMA module is a controller capable of performing complex data movements via 16 programmable
channels, with minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual data movement
operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor