PXD20RM Datasheet, PDF (1337/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

SGM Register Base + 0x0010 (Channel 3)
SGM Register Base + 0x0038 (Channel 2)
SGM Register Base + 0x0060 (Channel 1)
SGM Register Base + 0x0088 (Channel 0)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
DDSF
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-6. DDS Configuration Register for Channel 3 (DDSCH3)
Field
31-16
DDSF
15-0
Table 39-9. DDSCH3 Register Description
Description
Accumulator increment value for DDS Channel 3.
DDSF is added to the wavetable memory pointer every clock cycle. It therefore controls the frequency of the
sound. If DDSF is set to all 0’s, no sound will generated.
Reserved.
39.6.2.6 Envelope Configuration Register of Attack Phase for Channel 3
(ECRACH3)
The ECRACH3 register controls the envelope shape for the Attack phase of Channel 3.
SGM Register Base + 0x0014 (Channel 3)
SGM Register Base + 0x003C (Channel 2)
SGM Register Base + 0x0064 (Channel 1)
SGM Register Base + 0x008C (Channel 0)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ATKT
W
ATKSL
Reset 1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ATKSC
W
Reset 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Figure 39-7. Envelope Configuration Register of Attack Phase for Channel 3 (ECRACH3)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
39-13