PXD20RM Datasheet, PDF (591/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 13-9. Timing parameters (continued)
Controls JEDEC
Timing parameter
parameter
(JEDEC spec)
Formulae
(all times in system bus
clock periods)
Description
CCD_OTHER⁵
WTR1_OTHER⁵
—
CCD_OTHER =
CAS to CAS delay from one chip select to the other
max(t_CCD,2) (32-bit mode) +1 Because time is needed for data to be sent over,
max(t_CCD,4)(16-bit mode) +1 this time is minimum 2 clocks in 32-bit mode, 4
clocks in 16-bit mode
WTR1_OTHER =
WL - RL + 2 + 2(32-bit mode)
WL - RL + 4 + 2(16-bit mode)
Write to read time for write and read happening on
different chip selects, measured in clocks between
write command and read command. For this
reason, WL (the write latency) and the length of the
actual write (2 or 4) need to be added to t_WTR.
Figure 13-9 gives the details.
1 _{For DRAMs that do not need this check, set equal to 4 × tRRD}
2 _{For DDR1 and Mobile-DDR tCCD is 2 for 32-bit operation, 4 for 16-bit operation.}
3 _{For DDR1 and Mobile-DDR mode, tRTP is not explicitly given. It is equal to 4 for 16-bit mode, equal to 2 for 32-bit mode.}
4 _{This timing parameter controls precharge all command period duration. The equations shown are the JEDEC definition of the}
t_RPA. Some DRAM vendors do not follow JEDEC on this, and list t_RPA directly. In this case, set DRAM_TIME_RPA = t_RPA.
5 _{Field is part of register 0x60, dram_extra_attributes}
DRAM_CLK
DRAM_TIME_RTP
DRAM_COMMAND READ
NOP
NOP PRECHG
DRAM_ADDRESS Bank A
Bank A
DRAM_DQS
DRAM_DQ
D1 D2 D3 D4
Figure 13-7. Read to Precharge Timing Diagram
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
13-11