PXD20RM Datasheet, PDF (860/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 21-2 illustrates flash access and protection by master. Note that PFAPR’s initial value is loaded from
shadow flash location 0x3E00 after reset. The “Master” numbers correspond to the crossbar masters,
which for this device can be found in Table 9-1.
Table 21-2. Access and protection setting recommendations
Parameter
Parameter symbol in PFAPR
Comments
Arbitration Mode
Master n Prefetch Disable
Master n Access Protection
ARBM = 3
Start with round-bin (2 or 3).Change to
fixed priority if application analysis
indicates improved performance.
MnPFD = 0 for core instructions, eDMA
and DCU3; 1 for core data
Start with allowing prefetching (0) for
CPU instructions since it is expected the
core will have mostly sequential
instruction accesses. Also, allow
prefetching for eDMA and DCU3,
assuming there are large blocks of
graphic data accessed.
MnAP = 3 for core data, 1 for core
instructions, eDMA & DCU3
Assuming only the CPU will program
flash, allow read and write access (3) for
the CPU data bus, but read access only
(1) for CPU instructions, eDMA and
DCU3.
21-48
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor