PXD20RM Datasheet, PDF (818/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 21-1. Flash Memory Map (continued)
Offset from FLASH_BASE
(0x0000_0000)
Use
Block¹
0x00FF_C000–0x00FF_FDD7
General use
S
0x00FF_FDD8
Serial passcode (0xFEED_FACE_CAFE_BEEF)
0x00FF_FDE0
0x00FF_FDE4
Censorship control word (0x55AA_55AA)
General use
0x00FF_FDE8
0x00FF_FDEC
LML reset configuration (0x0010_0000)
General use
0x00FF_FDF0
0x00FF_FDF4
0x00FF_FDF8
HBL reset configuration (0x0FFF_FFFF)
General use
SLL reset configuration (0x000F_FFFF)
0x00FF_FDFC
0x00FF_FE00
0x00FF_FE04
0x00FF_FE08
0x00FF_FE0C
0x00FF_FE10
0x00FF_FE20 - 0x00FF_FFFF
General use
PFAPR reset configuration
General use
PFSACC reset configuration
General use
NVUSRO Register
General use
1 _{Ln = Low Address Space, Mn = Mid Address Space, Hn = High Address Space, S = Shadow Block.}
2 _{For read while write operations, the shadow row behaves as if it is in all partitions.}
Partition
All²
Table 21-2. Flash memory configuration register memory map
Offset from
FLASH_REGS_BASE
(0xC3F8_8000)
Register
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
MCR—Module configuration register
LML—Low-/Mid-address space block locking register
HBL—High-address space block locking register
SLL—Secondary low-/mid-address space block locking register
LMS—Low-/mid-address space block select register
HBS—High-address space block select register
ADR—Address register
PFCRP0—Platform flash configuration register for port 0
PFCRP1—Platform flash configuration register for port 1
PFAPR—Platform flash access protection register
PFSACC—Platform flash supervisor access control register
PFDACC—Platform flash data access control register
Location
on page 21-7
on page 21-11
on page 21-12
on page 21-13
on page 21-14
on page 21-15
on page 21-16
on page 21-17
on page 21-17
on page 21-20
on page 21-21
on page 21-23
21-6
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor