PXD20RM Datasheet, PDF (1399/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

40.8 Initialization and application information
To use the SRAM, the ECC must check all bits that require initialization after power on. Use a 64-bit
cache-inhibited write to each SRAM location to initialize the SRAM array as part of the application
initialization code. All writes must specify an even number of registers performed on 64-bit word-aligned
boundaries. If the write is not the entire 64 bits (e.g., 8, 16, or 32 bits), a read / modify / write operation is
generated that checks the ECC value upon the read. See Section 40.5, SRAM ECC mechanism.
NOTE
You must initialize SRAM, even if the application does not use ECC
reporting.
40.8.1 Example code
To initialize SRAM correctly, use a store multiple word (stmw) instruction to implement 64-bit writes to
all SRAM locations. The stmw instruction concatenates two 32-bit registers to implement a single 64-bit
write. To ensure the writes are 64-bits, specify an even number of registers and write on 64-bit
word-aligned boundaries.
The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits.
Example 40-1. Initializing SRAM ECC bits
init_RAM:
lis
r11,0x4000
ori
r11,r11,0
li
r12,640
mtctr r12
init_ram_loop:
stmw
r0,0(r11)
addi
r11,r11,128
bdnz
init_ram_loop
# base address of the SRAM, 64-bit word aligned
# not needed for this address but could be for others
# loop counter to get all of SRAM;
# 80k/4 bytes/32 GPRs = 640
# write all 32 GPRs to SRAM
# inc the ram ptr; 32 GPRs * 4 bytes = 128
# loop for 80k of SRAM
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
40-5