PXD20RM Datasheet, PDF (623/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• The particular channel has been configured to look at the DCU incoming priority, and the DCU
incoming priority is 8 or higher.
• The particular channel has been configured to look at the congestion monitor, and this block
indicates the multi-port DRAM is congested.
14.5.2 Description of operation — block diagram
A block diagram of the block is given in Figure 14-33.
20
Read or write on
any channel OR
en
idle pulse
28 DCU priority[3:0]
29
DCU overrule
63-bit
1
2
Own channel
21 ^{serviced OR}
Own channel
not requesting
Data
in
Combinatorial
logic
3
22 ack_count
4
5
8
+
LUT
D
1
chan_priority
0
[3:0] 30
6
7
01
Only DCU channel
1
alternate LUT 27
main LUT 26
LUT sel 26
Congested 24
DCU priority 23
Figure 14-33. Priority channel block diagram
Shift register 1 shifts in information of the recent ACK’s. Its a 63-stage shift register, so it contains
information on the last 63 bus cycles of the DRAMC.
The shift register is shifted any time a read or write request has been granted to the DRAM. (An ACK to
the requesting bus), or when there is an idle_pulse. An idle pulse is generated every time the DRAM is idle
for 4 consecutive clock cycles. Idle means none of the 5 incoming busses is making a request.
The shift data in is the corrected ACK for the self channel. If the shift register shifts because the current
cycle is granted to the “self” channel, a ‘1’ is shifted in, if not a ‘0’ is shifted in. It always occurs like this
when the own channel is requesting access. However, if the own channel is not requesting access,
depending on control bit ack_sel, a ‘1’ or a ‘0’ is shifted in. If ack_sel is ‘1’, a ‘1’ will be shifted in all the
time when the self channel is not requesting, and there is an ACK on any other channel, or there is an idle
pulse. If ack_sel is ‘0’, zeros are shifted in.
The correction for the non-requesting channel allows the user to steer the “default” priority, i.e., the
priority that the channel will get, when it has not been requesting for some time. If ack_sel is set ‘1’, the
default priority will be low. This setting is appropriate for peripherals with (large) FIFO’s. When they are
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
14-23