PXD20RM Datasheet, PDF (895/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 24-6. e200z0 OnCE Register Addressing (continued)
RS[0:6]
010 0111
010 1000 – 010 1111
011 0000
011 0001
011 0010
011 0011
011 0100 – 101 1111
110 1111
111 0000 – 111 1001
111 1010 – 111 1011
111 1100
111 1101
111 1110
111 1111
Register Selected
Data Value Compare 2 (DVC2)
Reserved
Debug Status Register (DBSR)
Debug Control Register 0 (DBCR0)
Debug Control Register 1 (DBCR1)
Debug Control Register 2 (DBCR2)
Reserved (do not access)
Reserved (do not access)
General Purpose Register Selects [0:9]
Reserved
Nexus2+ Access
LSRL Select
(factory test use only)
Enable_OnCE
Bypass
24.10 Initialization/Application Information
The test logic is a static logic design, and TCK can be stopped in either a high or low state without loss of
data. However, the system clock is not synchronized to TCK internally. Any mixed operation using both
the test logic and the system functional logic requires external synchronization.
To initialize the JTAGC module and enable access to registers, the following sequence is required:
1. Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS
2. Load the appropriate instruction for the test or action to be performed.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
24-13