PXD20RM Datasheet, PDF (624/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

not requesting, the FIFO is quite full, and when they do get on the bus, its OK for them to start with low
priority, and escalate to higher after some time.
Setting ack_sel to ‘0’ is appropriate for peripherals that desire high priority. The e200z4d and GFX2D
GPU are in this case. When they are not on the bus, its because they find the instruction or data that they
need in the processor caches, so they don’t request. When the cache misses, the request comes on the bus,
and need to be serviced fast. Therefore, ack_sel is set ‘0’, the default priority will be high, and servicing
fast. If e200z4d and/or GFX2D get on the bus a lot (e.g. due to a lot of cache swapping), the priority
manager will detect this, and degrade their priorities over time, so the other masters still get their fair share
of bus bandwidth.
The output of the shift register ANDED in 2 to look at only the last N ACK’s. Combinatorial logic 3
decodes the AND-ing code from register field ack_count. The number of ones after the AND-ing is added
up in adder 4, and saturated, so that the result out of adder 4 is a number in the range of 0 to 15. This number
is input in the look-up table 5. Table look-up content is taken for e.g. channel 1 from register LUT 1
main[63:0] or LUT 1 alternate[63:0]. Because of the 64-bit nature of the registers, actually 4 32-bit
registers are involved, whose description is given in Figure 14-6, Figure 14-7, Figure 14-8, and
Figure 14-9.
Selection on whether to use the “main” or the “alternate” register, is done via MUX 6. The MUX condition
has 2 possible sources again, selected by MUX 7, by means of control bit LUT sel, described in register
prioman_config, with details in Figure 14-3.
If LUT sel is ‘1’, alternate table is selected when the multi-port controller is congested. If LUT sel is ‘0’,
alternate table is selected when DCU incoming priority is higher than 8.
Pipeline register 8 is present purely for implementation reasons. It has no algorithmic function.
For the DCU, an additional bypass mux 9 is present. It overrules the prioman logic, and inserts the
incoming DCU priority in the output, if control bit DCU overrule is set. This bit is present in register
prioman_config, with details in Figure 14-3.
14.5.3 Congestion detector
The congestion detectors purpose is to detect when the DRAMC is congested. Congestion is assumed if
the share of the requests with priorities equal or greater than 8 is more than a certain percentage. If
congestion occurs, the priority manager may react by exchanging the look-up tables with the alternate
look-up tables, and in this way, reduce the average priority of the incoming requests. The reduced priorities
mean that on average, every incoming channel gets a lower priority, and the DRAMC will try harder to
optimize on bandwidth, and less to optimize to service the high-priority requests first. The switch-over is
driven by the congestion state. If many requests come in on “high priority,” so they all need to be serviced
“first,” the “congested” flag goes high, and the controller reacts to this by reducing the request priorities
(by switching in the alternate tables), so it can concentrate on the ones that are “really” important, and get
room again to optimized bandwidth.
14-24
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor