PXD20RM Datasheet, PDF (1092/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

These registers select the configurations during run and non-run modes for each peripheral.
Table 29-15. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions
Field
DBG_F
Description
Peripheral control in debug mode — This bit controls the state of the peripheral in debug mode
0 Peripheral state depends on RUN_CFG/LP_CFG bits and the device mode
1 Peripheral is frozen if not already frozen in device modes.
LP_CFG
RUN_CFG
Note: This feature is useful to freeze the peripheral state while entering debug. For example, this may
be used to prevent a reference timer from running while making a debug accesses.
Peripheral configuration select for non-run modes — These bits associate a configuration as
defined in the ME_LP_PC0…7 registers to the peripheral.
000 Selects ME_LP_PC0 configuration
001 Selects ME_LP_PC1 configuration
010 Selects ME_LP_PC2 configuration
011 Selects ME_LP_PC3 configuration
100 Selects ME_LP_PC4 configuration
101 Selects ME_LP_PC5 configuration
110 Selects ME_LP_PC6 configuration
111 Selects ME_LP_PC7 configuration
Peripheral configuration select for run modes — These bits associate a configuration as defined
in the ME_RUN_PC0…7 registers to the peripheral.
000 Selects ME_RUN_PC0 configuration
001 Selects ME_RUN_PC1 configuration
010 Selects ME_RUN_PC2 configuration
011 Selects ME_RUN_PC3 configuration
100 Selects ME_RUN_PC4 configuration
101 Selects ME_RUN_PC5 configuration
110 Selects ME_RUN_PC6 configuration
111 Selects ME_RUN_PC7 configuration
29.4 Functional description
29.4.1 Mode Transition Request
The transition from one mode to another mode is normally handled by software by accessing the mode
control register ME_MCTL. But the in case of special events, the mode transition can be automatically
managed by hardware. In order to switch from one mode to another, the application should access the
ME_MCTL register twice by writing
• The first time with the value of the key (0x5AF0) into the KEY bit field and the required target
mode into the TARGET_MODE bit field,
• And the second time with the inverted value of the key (0xA50F) into the KEY bit field and the
required target mode into the TARGET_MODE bit field.
Once a valid mode transition request is detected, the target mode configuration information is loaded from
the corresponding ME_<mode>_MC register. The mode transition request may require a number of cycles
depending on the programmed configuration, and software should check the S_CURRENT_MODE bit
field and the S_MTRANS bit of the global status register ME_GS to verify when the mode has been
29-34
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor