PXD20RM Datasheet, PDF (859/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Configuring the flash bus interface parameters is done by writing to the Platform Flash Configuration
Registers PFCRP0:1 and Platform Flash Access Protection Register PFAPR.
21.6.2 Flash memory setting recommendations
Table 21-1 provides an example of recommended settings for a common scenario with this device. This
example assumes Port 0 (core) instruction accesses are typically sequential, but not data. Port 1 (other
masters) will not have any instruction accesses. For illustration, this example assumes port 1 accesses have
a significant amount of sequential data (such as for graphics) which are larger than a line buffer, so
prefetching data would make sense. If graphic data were not in the internal flash, then prefetching data on
port 1 would not be expected to be a benefit.
Table 21-1. General flash memory setting recommendations for 125 MHz system clock
General recommendations
Parameter
Line Buffer
Configuration
Port 0 (CPU instruction only)
Parameter symbol in
register PFCR0
Comments
BFEN = 1
Enable port’s buffers
Port 1 (CPU data, other masters)
Parameter symbol
in register PFCR1
Comments
BFEN = 1
Enable port’s buffers
Instruction
IPFEN = 1
Prefetch Enable
Instructions are mostly
IPFEN = 0
sequential so prefeching can
improve performance.
No instruction access on port
1
Data Prefetch
Enable
DPFEN = 0
Data accesses are expected DPFEN = 1
to generally be random not
sequential
Enable prefetching
assuming there is significant
sequential data
Prefetch Limit PFLIM = 3
Prefetch on hit or miss
PFLIM = 1
Line Buffer
Configuration
LBCFG = 3
Allocate 3 line buffers for
instructions, 1 for data
LBCFG = 0
Read Wait States RWSC = 3
Values are system clock
frequency dependent
RWSC = 3
Write Wait States WWSC = 3
WWSC = 3
Adv. Pipeline Ctl. APC = 3
APC = 3
Result value for recommendations in PFCR0 = 0x3001_7B17, PFCR1 = 0x007C_7B43
Prefetch on miss only (allows
more bandwidth for core)
All 4 line buffers available for
any access
Values are system clock
frequency dependent
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-47