PXD20RM Datasheet, PDF (407/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
0
WEN_DISP
4
SLB_DISP
Table 11-53. Soft Lock DISP_SIZE Register Field Descriptions
Description
Write Enable for Soft Lock Bit SLB_DISP
1’b1: Value is written to SLB
1’b0: SLB is not modified
Soft Lock Bit for DISP_SIZE Register. This bit cannot be cleared once set by software. Can only
be cleared by system reset.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
11.3.4.49 Soft Lock HSYNC/VSYNC PARA Register
Figure 11-59 represents the Soft Lock HSYNC/VSYNC register.
Offset: 0x310
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0
0000000000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-59. Soft Lock HSYNC/VSYNC PARA Register
Table 11-54. Soft Lock HSYNC/VSYNC PARA Register Field Descriptions
Field
0
WEN_HSYNC
1
WEN_VSYNC
4
SLB_HSYNC
5
SLB_VSYNC
Description
Write Enable for Soft Lock Bit SLB_HSYNC
1’b1: Value is written to SLB
1’b0: SLB is not modified
Write Enable for Soft Lock Bit SLB_VSYNC
1’b1: Value is written to SLB
1’b0: SLB is not modified
Soft Lock Bit for HSYNC Register.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
Soft Lock Bit for VSYNC Register.
1’b1: Associated protected register is locked for write access
1’b0: Associated protected register is not locked & writeable
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-73