PXD20RM Datasheet, PDF (239/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
16
FM_EN
17-31
INC_STEP
Table 8-32. MR field descriptions (continued)
Description
Frequency Modulation Enable
The FM_EN enables the frequency modulation.
0 = Frequency Modulation disabled
1= Frequency Modulation enabled
Increment step
The INC_STEP field is the binary equivalent of the value incstep derived from following
formula:
incstep
=
r
ou
nd


1^---0^---2-0^---1-^{-5----–5----}^1-----M^------O^-m---D^--d---P^----E^--M--R^----DI---O^--F--D^{---}
where:
md: represents the peak modulation depth in percentage (Center spread -- pk-pk=+/-md,
Downspread -- pk-pk=-2*md)
MDF: represents the nominal value of loop divider (NDIV in PLL Control Register)
8.5.6 Functional description
8.5.6.1 Normal mode
In Normal Mode the PLL inputs are driven by the CR (see Section 8.5.5.1, Control register (CR)). This
means that, when the PLL is in lock state, the PLL output clock (PHI) is derived by the reference clock
(CLKIN) through Equation 8-1:
phi= ^c--_R--^l--^k-_I--_Nⁱ--ⁿ-_P---^-_--^R-_R----^L-_O--^O-_U---^O-_T--^P-
Eqn. 8-1
where the value of R_LOOP, R_INP, and R_OUT are set in the CR and can be derived from Table 8-28,
Table 8-29, and Table 8-30. Some examples are given in Table 8-33.
Table 8-33. Examples of typical PLL settings
Crystal
Frequency
(MHz)
8
PLL Output
Frequency
(MHz)
32
64
80
124
DRAM clock
Frequency
(MHz)
64
128
160
248
Register Values
IDF ODF NDIV
VCO
Frequency
(MHz)
0
1
32
256
0
1
64
512
0
0
40
320
0
0
62
496
16
32
64
80
124
64
0
1
32
256
128
0
1
64
512
160
0
0
40
320
248
0
0
62
496
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-43